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comparison FXAnalyse.c @ 23:65e277fdf01f

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Correct DDS3 frequency adjustement on N3 measurement We need to take into account the phase locked loop divisor factor that links DDS1 frequency change to repetition rate change.
author Daniele Nicolodi <daniele.nicolodi@obspm.fr>
date Fri, 20 Jul 2012 16:50:11 +0200
parents b7b3b5f1c5a6
children b838371c7a91
comparison
equal deleted inserted replaced
22:b7b3b5f1c5a6 23:65e277fdf01f
1220 1220
1221 // frep positive step 1221 // frep positive step
1222 SetCtrlVal(MainPanel, PANEL_DDS4, FrequDDS4 + DeltakHz_3 * 1000); 1222 SetCtrlVal(MainPanel, PANEL_DDS4, FrequDDS4 + DeltakHz_3 * 1000);
1223 DDS4xAD9912_SetFrequency(&DDS4xAD9912, 4, FrequDDS4 + DeltakHz_3 * 1000); 1223 DDS4xAD9912_SetFrequency(&DDS4xAD9912, 4, FrequDDS4 + DeltakHz_3 * 1000);
1224 // compensate with DDS3 to keep measured beatnote in counter box range 1224 // compensate with DDS3 to keep measured beatnote in counter box range
1225 double fDDS3 = FrequencyDDS3Init + N3/N1 * DeltakHz_3; 1225 double fDDS3 = FrequencyDDS3Init + N3/N1 * Ndiv * DeltakHz_3;
1226 SetCtrlVal(MainPanel, PANEL_DDS3, fDDS3); 1226 SetCtrlVal(MainPanel, PANEL_DDS3, fDDS3);
1227 DDS4xAD9912_SetFrequency(&DDS4xAD9912, 3, fDDS3); 1227 DDS4xAD9912_SetFrequency(&DDS4xAD9912, 3, fDDS3);
1228 // allow counter to settle 1228 // allow counter to settle
1229 settling = 3; 1229 settling = 3;
1230 } 1230 }
1252 1252
1253 // frep negative step 1253 // frep negative step
1254 SetCtrlVal(MainPanel, PANEL_DDS4, FrequDDS4 - DeltakHz_3 * 1000); 1254 SetCtrlVal(MainPanel, PANEL_DDS4, FrequDDS4 - DeltakHz_3 * 1000);
1255 DDS4xAD9912_SetFrequency(&DDS4xAD9912, 4, FrequDDS4 - DeltakHz_3 * 1000); 1255 DDS4xAD9912_SetFrequency(&DDS4xAD9912, 4, FrequDDS4 - DeltakHz_3 * 1000);
1256 // compensate with DDS3 to keep measured beatnote in counter box range 1256 // compensate with DDS3 to keep measured beatnote in counter box range
1257 double fDDS3 = FrequencyDDS3Init - N3/N1 * DeltakHz_3; 1257 double fDDS3 = FrequencyDDS3Init - N3/N1 * Ndiv * DeltakHz_3;
1258 SetCtrlVal(MainPanel, PANEL_DDS3, fDDS3); 1258 SetCtrlVal(MainPanel, PANEL_DDS3, fDDS3);
1259 DDS4xAD9912_SetFrequency(&DDS4xAD9912, 3, fDDS3); 1259 DDS4xAD9912_SetFrequency(&DDS4xAD9912, 3, fDDS3);
1260 // allow counter to settle 1260 // allow counter to settle
1261 settling = 3; 1261 settling = 3;
1262 } 1262 }