comparison m-toolbox/sltpda/test/test_resample.mdl @ 0:f0afece42f48

Import.
author Daniele Nicolodi <nicolodi@science.unitn.it>
date Wed, 23 Nov 2011 19:22:13 +0100
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children
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-1:000000000000 0:f0afece42f48
1 Model {
2 Name "test_resample"
3 Version 6.6
4 MdlSubVersion 0
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39 BrowserShowLibraryLinks off
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41 Created "Sat Apr 7 19:33:16 2007"
42 Creator "hewitson"
43 UpdateHistory "UpdateHistoryNever"
44 ModifiedByFormat "%<Auto>"
45 LastModifiedBy "hewitson"
46 ModifiedDateFormat "%<Auto>"
47 LastModifiedDate "Sat Apr 7 19:39:52 2007"
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555 System {
556 Name "test_resample"
557 Location [239, 199, 819, 459]
558 Open on
559 ModelBrowserVisibility off
560 ModelBrowserWidth 200
561 ScreenColor "white"
562 PaperOrientation "landscape"
563 PaperPositionMode "auto"
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580 Block {
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582 Name "Signal Generator"
583 Tag "ao"
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585 Position [80, 56, 130, 104]
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588 SourceType "ao"
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594 RTWMemSecDataConstants "Inherit from model"
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596 RTWMemSecDataParameters "Inherit from model"
597 nsecs "10"
598 fs "100"
599 tsfcn "sin(2*pi*0.3*t)"
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601 Block {
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616 RTWMemSecDataParameters "Inherit from model"
617 }
618 Block {
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621 Tag "get"
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626 SourceBlock "sltpda/AO class/get"
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629 SystemSampleTime "-1"
630 FunctionWithSeparateData off
631 RTWMemSecFuncInitTerm "Inherit from model"
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637 }
638 Block {
639 BlockType Reference
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645 AttributesFormatString "%<Tag>"
646 SourceBlock "sltpda/AO class/plot"
647 SourceType "plot"
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650 FunctionWithSeparateData off
651 RTWMemSecFuncInitTerm "Inherit from model"
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653 RTWMemSecDataConstants "Inherit from model"
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655 RTWMemSecDataParameters "Inherit from model"
656 xscale "linear"
657 yscale "linear"
658 }
659 Block {
660 BlockType Reference
661 Name "resample"
662 Tag "resample"
663 Ports [1, 1]
664 Position [225, 60, 300, 100]
665 SourceBlock "sltpda/Signal Processing blocks/resample"
666 SourceType "resample"
667 ShowPortLabels "FromPortIcon"
668 SystemSampleTime "-1"
669 FunctionWithSeparateData off
670 RTWMemSecFuncInitTerm "Inherit from model"
671 RTWMemSecFuncExecute "Inherit from model"
672 RTWMemSecDataConstants "Inherit from model"
673 RTWMemSecDataInternal "Inherit from model"
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675 fsout "128"
676 }
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680 Points [55, 0]
681 Branch {
682 DstBlock "resample"
683 DstPort 1
684 }
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688 DstPort 2
689 }
690 }
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696 DstPort 1
697 }
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716 }
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718 }