Mercurial > hg > ltpda

comparison m-toolbox/sltpda/test/timedomain_fit.mdl @ 0:f0afece42f48

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author Daniele Nicolodi <nicolodi@science.unitn.it>
date Wed, 23 Nov 2011 19:22:13 +0100
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-1:000000000000 0:f0afece42f48
1 Model {
2 Name "timedomain_fit"
3 Version 6.6
4 MdlSubVersion 0
5 GraphicalInterface {
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7 NumRootOutports 0
8 ParameterArgumentNames ""
9 ComputedModelVersion "1.18"
10 NumModelReferences 0
11 NumTestPointedSignals 0
12 }
13 SavedCharacterEncoding "ISO-8859-1"
14 SaveDefaultBlockParams on
15 SampleTimeColors off
16 LibraryLinkDisplay "none"
17 WideLines off
18 ShowLineDimensions off
19 ShowPortDataTypes off
20 ShowLoopsOnError on
21 IgnoreBidirectionalLines off
22 ShowStorageClass off
23 ShowTestPointIcons on
24 ShowViewerIcons on
25 SortedOrder off
26 ExecutionContextIcon off
27 ShowLinearizationAnnotations on
28 ScopeRefreshTime 0.035000
29 OverrideScopeRefreshTime on
30 DisableAllScopes off
31 DataTypeOverride "UseLocalSettings"
32 MinMaxOverflowLogging "UseLocalSettings"
33 MinMaxOverflowArchiveMode "Overwrite"
34 BlockNameDataTip off
35 BlockParametersDataTip off
36 BlockDescriptionStringDataTip off
37 ToolBar on
38 StatusBar on
39 BrowserShowLibraryLinks off
40 BrowserLookUnderMasks off
41 Created "Wed Mar 28 13:49:56 2007"
42 Creator "hewitson"
43 UpdateHistory "UpdateHistoryNever"
44 ModifiedByFormat "%<Auto>"
45 LastModifiedBy "hewitson"
46 ModifiedDateFormat "%<Auto>"
47 LastModifiedDate "Tue Apr 3 15:06:33 2007"
48 ModelVersionFormat "1.%<AutoIncrement:18>"
49 ConfigurationManager "cvs"
50 SimulationMode "normal"
51 LinearizationMsg "none"
52 Profile off
53 ParamWorkspaceSource "MATLABWorkspace"
54 AccelSystemTargetFile "accel.tlc"
55 AccelTemplateMakefile "accel_default_tmf"
56 AccelMakeCommand "make_rtw"
57 AccelVerboseBuild off
58 TryForcingSFcnDF off
59 RecordCoverage off
60 CovPath "/"
61 CovSaveName "covdata"
62 CovMetricSettings "dw"
63 CovNameIncrementing off
64 CovHtmlReporting on
65 covSaveCumulativeToWorkspaceVar on
66 CovSaveSingleToWorkspaceVar on
67 CovCumulativeVarName "covCumulativeData"
68 CovCumulativeReport off
69 CovReportOnPause on
70 ExtModeBatchMode off
71 ExtModeEnableFloating on
72 ExtModeTrigType "manual"
73 ExtModeTrigMode "normal"
74 ExtModeTrigPort "1"
75 ExtModeTrigElement "any"
76 ExtModeTrigDuration 1000
77 ExtModeTrigDurationFloating "auto"
78 ExtModeTrigHoldOff 0
79 ExtModeTrigDelay 0
80 ExtModeTrigDirection "rising"
81 ExtModeTrigLevel 0
82 ExtModeArchiveMode "off"
83 ExtModeAutoIncOneShot off
84 ExtModeIncDirWhenArm off
85 ExtModeAddSuffixToVar off
86 ExtModeWriteAllDataToWs off
87 ExtModeArmWhenConnect on
88 ExtModeSkipDownloadWhenConnect off
89 ExtModeLogAll on
90 ExtModeAutoUpdateStatusClock off
91 BufferReuse on
92 ProdHWDeviceType "32-bit Generic"
93 ShowModelReferenceBlockVersion off
94 ShowModelReferenceBlockIO off
95 Array {
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97 Dimension 1
98 Simulink.ConfigSet {
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100 Version "1.2.0"
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104 Simulink.SolverCC {
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106 Version "1.2.0"
107 StartTime "0.0"
108 StopTime "10.0"
109 AbsTol "auto"
110 FixedStep "auto"
111 InitialStep "auto"
112 MaxNumMinSteps "-1"
113 MaxOrder 5
114 ConsecutiveZCsStepRelTol "10*128*eps"
115 MaxConsecutiveZCs "1000"
116 ExtrapolationOrder 4
117 NumberNewtonIterations 1
118 MaxStep "auto"
119 MinStep "auto"
120 MaxConsecutiveMinStep "1"
121 RelTol "1e-3"
122 SolverMode "Auto"
123 Solver "ode45"
124 SolverName "ode45"
125 ZeroCrossControl "UseLocalSettings"
126 AlgebraicLoopSolver "TrustRegion"
127 SolverResetMethod "Fast"
128 PositivePriorityOrder off
129 AutoInsertRateTranBlk off
130 SampleTimeConstraint "Unconstrained"
131 RateTranMode "Deterministic"
132 }
133 Simulink.DataIOCC {
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135 Version "1.2.0"
136 Decimation "1"
137 ExternalInput "[t, u]"
138 FinalStateName "xFinal"
139 InitialState "xInitial"
140 LimitDataPoints on
141 MaxDataPoints "1000"
142 LoadExternalInput off
143 LoadInitialState off
144 SaveFinalState off
145 SaveFormat "Array"
146 SaveOutput on
147 SaveState off
148 SignalLogging on
149 InspectSignalLogs off
150 SaveTime on
151 StateSaveName "xout"
152 TimeSaveName "tout"
153 OutputSaveName "yout"
154 SignalLoggingName "logsout"
155 OutputOption "RefineOutputTimes"
156 OutputTimes "[]"
157 Refine "1"
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159 Simulink.OptimizationCC {
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163 Dimension 5
164 Cell "ZeroExternalMemoryAtStartup"
165 Cell "ZeroInternalMemoryAtStartup"
166 Cell "InitFltsAndDblsToZero"
167 Cell "OptimizeModelRefInitCode"
168 Cell "NoFixptDivByZeroProtection"
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171 Version "1.2.0"
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178 BufferReuse on
179 EnforceIntegerDowncast on
180 ExpressionFolding on
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183 LocalBlockOutputs on
184 RollThreshold 5
185 SystemCodeInlineAuto off
186 StateBitsets off
187 DataBitsets off
188 UseTempVars off
189 ZeroExternalMemoryAtStartup on
190 ZeroInternalMemoryAtStartup on
191 InitFltsAndDblsToZero on
192 NoFixptDivByZeroProtection off
193 EfficientFloat2IntCast off
194 OptimizeModelRefInitCode off
195 LifeSpan "inf"
196 BufferReusableBoundary on
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198 Simulink.DebuggingCC {
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200 Version "1.2.0"
201 RTPrefix "error"
202 ConsistencyChecking "none"
203 ArrayBoundsChecking "none"
204 SignalInfNanChecking "none"
205 ReadBeforeWriteMsg "UseLocalSettings"
206 WriteAfterWriteMsg "UseLocalSettings"
207 WriteAfterReadMsg "UseLocalSettings"
208 AlgebraicLoopMsg "warning"
209 ArtificialAlgebraicLoopMsg "warning"
210 CheckSSInitialOutputMsg on
211 CheckExecutionContextPreStartOutputMsg off
212 CheckExecutionContextRuntimeOutputMsg off
213 SignalResolutionControl "UseLocalSettings"
214 BlockPriorityViolationMsg "warning"
215 MinStepSizeMsg "warning"
216 TimeAdjustmentMsg "none"
217 MaxConsecutiveZCsMsg "error"
218 SolverPrmCheckMsg "warning"
219 InheritedTsInSrcMsg "warning"
220 DiscreteInheritContinuousMsg "warning"
221 MultiTaskDSMMsg "error"
222 MultiTaskCondExecSysMsg "error"
223 MultiTaskRateTransMsg "error"
224 SingleTaskRateTransMsg "none"
225 TasksWithSamePriorityMsg "warning"
226 SigSpecEnsureSampleTimeMsg "warning"
227 CheckMatrixSingularityMsg "none"
228 IntegerOverflowMsg "warning"
229 Int32ToFloatConvMsg "warning"
230 ParameterDowncastMsg "error"
231 ParameterOverflowMsg "error"
232 ParameterUnderflowMsg "none"
233 ParameterPrecisionLossMsg "warning"
234 ParameterTunabilityLossMsg "warning"
235 UnderSpecifiedDataTypeMsg "none"
236 UnnecessaryDatatypeConvMsg "none"
237 VectorMatrixConversionMsg "none"
238 InvalidFcnCallConnMsg "error"
239 FcnCallInpInsideContextMsg "Use local settings"
240 SignalLabelMismatchMsg "none"
241 UnconnectedInputMsg "warning"
242 UnconnectedOutputMsg "warning"
243 UnconnectedLineMsg "warning"
244 SFcnCompatibilityMsg "none"
245 UniqueDataStoreMsg "none"
246 BusObjectLabelMismatch "warning"
247 RootOutportRequireBusObject "warning"
248 AssertControl "UseLocalSettings"
249 EnableOverflowDetection off
250 ModelReferenceIOMsg "none"
251 ModelReferenceVersionMismatchMessage "none"
252 ModelReferenceIOMismatchMessage "none"
253 ModelReferenceCSMismatchMessage "none"
254 ModelReferenceSimTargetVerbose off
255 UnknownTsInhSupMsg "warning"
256 ModelReferenceDataLoggingMessage "warning"
257 ModelReferenceSymbolNameMessage "warning"
258 ModelReferenceExtraNoncontSigs "error"
259 StateNameClashWarn "warning"
260 StrictBusMsg "Warning"
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262 Simulink.HardwareCC {
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264 Version "1.2.0"
265 ProdBitPerChar 8
266 ProdBitPerShort 16
267 ProdBitPerInt 32
268 ProdBitPerLong 32
269 ProdIntDivRoundTo "Undefined"
270 ProdEndianess "Unspecified"
271 ProdWordSize 32
272 ProdShiftRightIntArith on
273 ProdHWDeviceType "32-bit Generic"
274 TargetBitPerChar 8
275 TargetBitPerShort 16
276 TargetBitPerInt 32
277 TargetBitPerLong 32
278 TargetShiftRightIntArith on
279 TargetIntDivRoundTo "Undefined"
280 TargetEndianess "Unspecified"
281 TargetWordSize 32
282 TargetTypeEmulationWarnSuppressLevel 0
283 TargetPreprocMaxBitsSint 32
284 TargetPreprocMaxBitsUint 32
285 TargetHWDeviceType "Specified"
286 TargetUnknown off
287 ProdEqTarget on
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291 Version "1.2.0"
292 UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
293 CheckModelReferenceTargetMessage "error"
294 ModelReferenceNumInstancesAllowed "Multi"
295 ModelReferencePassRootInputsByReference on
296 ModelReferenceMinAlgLoopOccurrences off
297 }
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304 Cell "IncludeHyperlinkInReport"
305 PropName "DisabledProps"
306 }
307 Version "1.2.0"
308 SystemTargetFile "grt.tlc"
309 GenCodeOnly off
310 MakeCommand "make_rtw"
311 GenerateMakefile on
312 TemplateMakefile "grt_default_tmf"
313 GenerateReport off
314 SaveLog off
315 RTWVerbose on
316 RetainRTWFile off
317 ProfileTLC off
318 TLCDebug off
319 TLCCoverage off
320 TLCAssert off
321 ProcessScriptMode "Default"
322 ConfigurationMode "Optimized"
323 ConfigAtBuild off
324 IncludeHyperlinkInReport off
325 LaunchReport off
326 TargetLang "C"
327 IncludeBusHierarchyInRTWFileBlockHierarchyMap off
328 IncludeERTFirstTime off
329 Array {
330 Type "Handle"
331 Dimension 2
332 Simulink.CodeAppCC {
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339 Cell "SFDataObjDesc"
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342 Cell "SignalNamingRule"
343 Cell "ParamNamingRule"
344 Cell "InlinedPrmAccess"
345 Cell "CustomSymbolStr"
346 Cell "CustomSymbolStrGlobalVar"
347 Cell "CustomSymbolStrType"
348 Cell "CustomSymbolStrField"
349 Cell "CustomSymbolStrFcn"
350 Cell "CustomSymbolStrBlkIO"
351 Cell "CustomSymbolStrTmpVar"
352 Cell "CustomSymbolStrMacro"
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355 Version "1.2.0"
356 ForceParamTrailComments off
357 GenerateComments on
358 IgnoreCustomStorageClasses on
359 IncHierarchyInIds off
360 MaxIdLength 31
361 PreserveName off
362 PreserveNameWithParent off
363 ShowEliminatedStatement off
364 IncAutoGenComments off
365 SimulinkDataObjDesc off
366 SFDataObjDesc off
367 IncDataTypeInIds off
368 PrefixModelToSubsysFcnNames on
369 MangleLength 1
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371 CustomSymbolStrType "$N$R$M"
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373 CustomSymbolStrFcn "$R$N$M$F"
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376 CustomSymbolStrMacro "$R$N$M"
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380 InsertBlockDesc off
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382 EnableCustomComments off
383 InlinedPrmAccess "Literals"
384 ReqsInCode off
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397 Cell "GenerateTestInterfaces"
398 Cell "ModelStepFunctionPrototypeControlComp"
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402 Cell "SupportNonFinite"
403 Cell "SupportComplex"
404 Cell "SupportAbsoluteTime"
405 Cell "SupportContinuousTime"
406 Cell "SupportNonInlinedSFcns"
407 Cell "PortableWordSizes"
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409 }
410 Version "1.2.0"
411 TargetFcnLib "ansi_tfl_tmw.mat"
412 TargetLibSuffix ""
413 TargetPreCompLibLocation ""
414 GenFloatMathFcnCalls "ANSI_C"
415 UtilityFuncGeneration "Auto"
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418 GenerateTestInterfaces off
419 IsPILTarget off
420 ModelReferenceCompliant on
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436 ParenthesesLevel "Nominal"
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438 ModelStepFunctionPrototypeControlCompliant off
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441 ExtModeTesting off
442 ExtModeStaticAllocSize 1000000
443 ExtModeTransport 0
444 ExtModeMexFile "ext_comm"
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452 }
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468 DropShadow off
469 NamePlacement "normal"
470 FontName "Helvetica"
471 FontSize 10
472 FontWeight "normal"
473 FontAngle "normal"
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475 }
476 BlockParameterDefaults {
477 Block {
478 BlockType Inport
479 Port "1"
480 UseBusObject off
481 BusObject "BusObject"
482 BusOutputAsStruct off
483 PortDimensions "-1"
484 SampleTime "-1"
485 DataType "auto"
486 OutDataType "sfix(16)"
487 OutScaling "2^0"
488 SignalType "auto"
489 SamplingMode "auto"
490 LatchByDelayingOutsideSignal off
491 LatchByCopyingInsideSignal off
492 Interpolate on
493 }
494 Block {
495 BlockType Mux
496 Inputs "4"
497 DisplayOption "none"
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501 }
502 Block {
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512 OutScaling "2^0"
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514 SamplingMode "auto"
515 OutputWhenDisabled "held"
516 InitialOutput "[]"
517 }
518 Block {
519 BlockType SubSystem
520 ShowPortLabels "FromPortIcon"
521 Permissions "ReadWrite"
522 PermitHierarchicalResolution "All"
523 TreatAsAtomicUnit off
524 SystemSampleTime "-1"
525 RTWFcnNameOpts "Auto"
526 RTWFileNameOpts "Auto"
527 RTWMemSecFuncInitTerm "Inherit from model"
528 RTWMemSecFuncExecute "Inherit from model"
529 RTWMemSecDataConstants "Inherit from model"
530 RTWMemSecDataInternal "Inherit from model"
531 RTWMemSecDataParameters "Inherit from model"
532 SimViewingDevice off
533 DataTypeOverride "UseLocalSettings"
534 MinMaxOverflowLogging "UseLocalSettings"
535 }
536 }
537 AnnotationDefaults {
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548 }
549 LineDefaults {
550 FontName "Helvetica"
551 FontSize 9
552 FontWeight "normal"
553 FontAngle "normal"
554 }
555 System {
556 Name "timedomain_fit"
557 Location [209, 257, 1052, 813]
558 Open on
559 ModelBrowserVisibility off
560 ModelBrowserWidth 200
561 ScreenColor "white"
562 PaperOrientation "landscape"
563 PaperPositionMode "auto"
564 PaperType "A4"
565 PaperUnits "inches"
566 TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
567 TiledPageScale 1
568 ShowPageBoundaries off
569 ZoomFactor "100"
570 ReportName "simulink-default.rpt"
571 Block {
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573 Name "Mux1"
574 Ports [6, 1]
575 Position [445, 141, 450, 249]
576 ShowName off
577 Inputs "6"
578 DisplayOption "bar"
579 }
580 Block {
581 BlockType Mux
582 Name "Mux2"
583 Ports [2, 1]
584 Position [610, 131, 615, 169]
585 ShowName off
586 Inputs "2"
587 DisplayOption "bar"
588 }
589 Block {
590 BlockType Reference
591 Name "eta1"
592 Tag "ao"
593 Description "Creates an Analysis object from a file."
594 Ports [0, 1]
595 Position [80, 158, 130, 192]
596 AttributesFormatString "%<Tag>"
597 SourceBlock "sltpda/AO class/ao1"
598 SourceType "ao"
599 ShowPortLabels "FromPortIcon"
600 SystemSampleTime "-1"
601 FunctionWithSeparateData off
602 RTWMemSecFuncInitTerm "Inherit from model"
603 RTWMemSecFuncExecute "Inherit from model"
604 RTWMemSecDataConstants "Inherit from model"
605 RTWMemSecDataInternal "Inherit from model"
606 RTWMemSecDataParameters "Inherit from model"
607 fname "/Users/hewitson/working/ltp/ltpda/software/m-to"
608 "olbox/sltpda/test/eta1.txt"
609 }
610 Block {
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613 Tag "ao"
614 Description "Creates an Analysis object from a file."
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618 SourceBlock "sltpda/AO class/ao1"
619 SourceType "ao"
620 ShowPortLabels "FromPortIcon"
621 SystemSampleTime "-1"
622 FunctionWithSeparateData off
623 RTWMemSecFuncInitTerm "Inherit from model"
624 RTWMemSecFuncExecute "Inherit from model"
625 RTWMemSecDataConstants "Inherit from model"
626 RTWMemSecDataInternal "Inherit from model"
627 RTWMemSecDataParameters "Inherit from model"
628 fname "/Users/hewitson/working/ltp/ltpda/software/m-to"
629 "olbox/sltpda/test/eta12.txt"
630 }
631 Block {
632 BlockType Reference
633 Name "ltpda_lincom"
634 Ports [1, 1]
635 Position [475, 168, 575, 222]
636 SourceBlock "sltpda/math blocks/ltpda_lincom"
637 SourceType "ltpda_lincom"
638 ShowPortLabels "FromPortIcon"
639 SystemSampleTime "-1"
640 FunctionWithSeparateData off
641 RTWMemSecFuncInitTerm "Inherit from model"
642 RTWMemSecFuncExecute "Inherit from model"
643 RTWMemSecDataConstants "Inherit from model"
644 RTWMemSecDataInternal "Inherit from model"
645 RTWMemSecDataParameters "Inherit from model"
646 coeffs "0"
647 }
648 Block {
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650 Name "ltpda_polydetrend"
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652 Ports [1, 1]
653 Position [555, 22, 640, 78]
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655 SourceBlock "sltpda/Signal Processing blocks/ltpda_polydetre"
656 "nd"
657 SourceType "ltpda_polydetrend"
658 ShowPortLabels "FromPortIcon"
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660 FunctionWithSeparateData off
661 RTWMemSecFuncInitTerm "Inherit from model"
662 RTWMemSecFuncExecute "Inherit from model"
663 RTWMemSecDataConstants "Inherit from model"
664 RTWMemSecDataInternal "Inherit from model"
665 RTWMemSecDataParameters "Inherit from model"
666 degree "1"
667 }
668 Block {
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670 Name "ltpda_pwelch"
671 Tag "ltpda_pwelch"
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678 SourceType "ltpda_pwelch"
679 ShowPortLabels "FromPortIcon"
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681 FunctionWithSeparateData off
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683 RTWMemSecFuncExecute "Inherit from model"
684 RTWMemSecDataConstants "Inherit from model"
685 RTWMemSecDataInternal "Inherit from model"
686 RTWMemSecDataParameters "Inherit from model"
687 win "Hanning"
688 nfft "6000"
689 psll "0"
690 nolap "0"
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700 SourceBlock "sltpda/AO class/ao1"
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702 ShowPortLabels "FromPortIcon"
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704 FunctionWithSeparateData off
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706 RTWMemSecFuncExecute "Inherit from model"
707 RTWMemSecDataConstants "Inherit from model"
708 RTWMemSecDataInternal "Inherit from model"
709 RTWMemSecDataParameters "Inherit from model"
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727 RTWMemSecFuncExecute "Inherit from model"
728 RTWMemSecDataConstants "Inherit from model"
729 RTWMemSecDataInternal "Inherit from model"
730 RTWMemSecDataParameters "Inherit from model"
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743 SourceType "plot"
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747 RTWMemSecFuncInitTerm "Inherit from model"
748 RTWMemSecFuncExecute "Inherit from model"
749 RTWMemSecDataConstants "Inherit from model"
750 RTWMemSecDataInternal "Inherit from model"
751 RTWMemSecDataParameters "Inherit from model"
752 xscale "linear"
753 yscale "linear"
754 }
755 Block {
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758 Tag "plot"
759 Description "Plot an analysis object."
760 Ports [1]
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762 AttributesFormatString "%<Tag>"
763 SourceBlock "sltpda/AO class/plot"
764 SourceType "plot"
765 ShowPortLabels "FromPortIcon"
766 SystemSampleTime "-1"
767 FunctionWithSeparateData off
768 RTWMemSecFuncInitTerm "Inherit from model"
769 RTWMemSecFuncExecute "Inherit from model"
770 RTWMemSecDataConstants "Inherit from model"
771 RTWMemSecDataInternal "Inherit from model"
772 RTWMemSecDataParameters "Inherit from model"
773 xscale "linear"
774 yscale "linear"
775 }
776 Block {
777 BlockType SubSystem
778 Name "time-domain fit"
779 Ports [5, 1]
780 Position [275, 69, 335, 131]
781 MinAlgLoopOccurrences off
782 RTWSystemCode "Auto"
783 FunctionWithSeparateData off
784 MaskHideContents off
785 System {
786 Name "time-domain fit"
787 Location [660, 177, 1280, 797]
788 Open on
789 ModelBrowserVisibility off
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791 ScreenColor "white"
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808 Name "In2"
809 Position [30, 158, 60, 172]
810 Port "2"
811 IconDisplay "Port number"
812 }
813 Block {
814 BlockType Inport
815 Name "In3"
816 Position [30, 268, 60, 282]
817 Port "3"
818 IconDisplay "Port number"
819 }
820 Block {
821 BlockType Inport
822 Name "In4"
823 Position [25, 373, 55, 387]
824 Port "4"
825 IconDisplay "Port number"
826 }
827 Block {
828 BlockType Inport
829 Name "In5"
830 Position [25, 488, 55, 502]
831 Port "5"
832 IconDisplay "Port number"
833 }
834 Block {
835 BlockType Mux
836 Name "Mux"
837 Ports [5, 1]
838 Position [410, 215, 415, 375]
839 ShowName off
840 Inputs "5"
841 DisplayOption "bar"
842 }
843 Block {
844 BlockType Reference
845 Name "Standard Filter"
846 Tag "filter"
847 Description "Apply a standard filter type to input AO."
848 Ports [1, 1]
849 Position [90, 32, 155, 78]
850 AttributesFormatString "%<Tag>\\n%<ftype>\\n%<ffc>\\n%<ffs>\\n%<fga"
851 "in>"
852 SourceBlock "sltpda/Signal Processing blocks/Standard Fi"
853 "lter"
854 SourceType "filter"
855 ShowPortLabels "FromPortIcon"
856 SystemSampleTime "-1"
857 FunctionWithSeparateData off
858 RTWMemSecFuncInitTerm "Inherit from model"
859 RTWMemSecFuncExecute "Inherit from model"
860 RTWMemSecDataConstants "Inherit from model"
861 RTWMemSecDataInternal "Inherit from model"
862 RTWMemSecDataParameters "Inherit from model"
863 method "filter"
864 ftype "bandpass"
865 fgain "1"
866 ffs "32.46"
867 ffc "0.003 0.03"
868 forder "2"
869 }
870 Block {
871 BlockType Reference
872 Name "Standard Filter1"
873 Tag "filter"
874 Description "Apply a standard filter type to input AO."
875 Ports [1, 1]
876 Position [95, 142, 160, 188]
877 AttributesFormatString "%<Tag>\\n%<ftype>\\n%<ffc>\\n%<ffs>\\n%<fga"
878 "in>"
879 SourceBlock "sltpda/Signal Processing blocks/Standard Fi"
880 "lter"
881 SourceType "filter"
882 ShowPortLabels "FromPortIcon"
883 SystemSampleTime "-1"
884 FunctionWithSeparateData off
885 RTWMemSecFuncInitTerm "Inherit from model"
886 RTWMemSecFuncExecute "Inherit from model"
887 RTWMemSecDataConstants "Inherit from model"
888 RTWMemSecDataInternal "Inherit from model"
889 RTWMemSecDataParameters "Inherit from model"
890 method "filter"
891 ftype "bandpass"
892 fgain "1"
893 ffs "32.46"
894 ffc "0.003 0.03"
895 forder "2"
896 }
897 Block {
898 BlockType Reference
899 Name "Standard Filter2"
900 Tag "filter"
901 Description "Apply a standard filter type to input AO."
902 Ports [1, 1]
903 Position [95, 247, 160, 293]
904 AttributesFormatString "%<Tag>\\n%<ftype>\\n%<ffc>\\n%<ffs>\\n%<fga"
905 "in>"
906 SourceBlock "sltpda/Signal Processing blocks/Standard Fi"
907 "lter"
908 SourceType "filter"
909 ShowPortLabels "FromPortIcon"
910 SystemSampleTime "-1"
911 FunctionWithSeparateData off
912 RTWMemSecFuncInitTerm "Inherit from model"
913 RTWMemSecFuncExecute "Inherit from model"
914 RTWMemSecDataConstants "Inherit from model"
915 RTWMemSecDataInternal "Inherit from model"
916 RTWMemSecDataParameters "Inherit from model"
917 method "filter"
918 ftype "bandpass"
919 fgain "1"
920 ffs "32.46"
921 ffc "0.003 0.03"
922 forder "2"
923 }
924 Block {
925 BlockType Reference
926 Name "Standard Filter3"
927 Tag "filter"
928 Description "Apply a standard filter type to input AO."
929 Ports [1, 1]
930 Position [90, 357, 155, 403]
931 AttributesFormatString "%<Tag>\\n%<ftype>\\n%<ffc>\\n%<ffs>\\n%<fga"
932 "in>"
933 SourceBlock "sltpda/Signal Processing blocks/Standard Fi"
934 "lter"
935 SourceType "filter"
936 ShowPortLabels "FromPortIcon"
937 SystemSampleTime "-1"
938 FunctionWithSeparateData off
939 RTWMemSecFuncInitTerm "Inherit from model"
940 RTWMemSecFuncExecute "Inherit from model"
941 RTWMemSecDataConstants "Inherit from model"
942 RTWMemSecDataInternal "Inherit from model"
943 RTWMemSecDataParameters "Inherit from model"
944 method "filter"
945 ftype "bandpass"
946 fgain "1"
947 ffs "32.46"
948 ffc "0.003 0.03"
949 forder "2"
950 }
951 Block {
952 BlockType Reference
953 Name "Standard Filter4"
954 Tag "filter"
955 Description "Apply a standard filter type to input AO."
956 Ports [1, 1]
957 Position [90, 467, 155, 513]
958 AttributesFormatString "%<Tag>\\n%<ftype>\\n%<ffc>\\n%<ffs>\\n%<fga"
959 "in>"
960 SourceBlock "sltpda/Signal Processing blocks/Standard Fi"
961 "lter"
962 SourceType "filter"
963 ShowPortLabels "FromPortIcon"
964 SystemSampleTime "-1"
965 FunctionWithSeparateData off
966 RTWMemSecFuncInitTerm "Inherit from model"
967 RTWMemSecFuncExecute "Inherit from model"
968 RTWMemSecDataConstants "Inherit from model"
969 RTWMemSecDataInternal "Inherit from model"
970 RTWMemSecDataParameters "Inherit from model"
971 method "filter"
972 ftype "bandpass"
973 fgain "1"
974 ffs "32.46"
975 ffc "0.003 0.03"
976 forder "2"
977 }
978 Block {
979 BlockType Reference
980 Name "ltpda_timedomainfit"
981 Tag "ltpda_timedomainfit"
982 Description "Performs a time-domain fit of the input AOs"
983 " using ltpda_timedomainfit."
984 Ports [1, 1]
985 Position [460, 267, 540, 323]
986 AttributesFormatString "%<Tag>"
987 SourceBlock "sltpda/Signal Processing blocks/ltpda_timed"
988 "omainfit"
989 SourceType "ltpda_timedomainfit"
990 ShowPortLabels "FromPortIcon"
991 SystemSampleTime "-1"
992 FunctionWithSeparateData off
993 RTWMemSecFuncInitTerm "Inherit from model"
994 RTWMemSecFuncExecute "Inherit from model"
995 RTWMemSecDataConstants "Inherit from model"
996 RTWMemSecDataInternal "Inherit from model"
997 RTWMemSecDataParameters "Inherit from model"
998 }
999 Block {
1000 BlockType Reference
1001 Name "split"
1002 Tag "split"
1003 Description "Splits an AO into many sub-AOs."
1004 Ports [1, 1]
1005 Position [180, 34, 245, 76]
1006 AttributesFormatString "%<Tag>"
1007 SourceBlock "sltpda/AO class/split"
1008 SourceType "split"
1009 ShowPortLabels "FromPortIcon"
1010 SystemSampleTime "-1"
1011 FunctionWithSeparateData off
1012 RTWMemSecFuncInitTerm "Inherit from model"
1013 RTWMemSecFuncExecute "Inherit from model"
1014 RTWMemSecDataConstants "Inherit from model"
1015 RTWMemSecDataInternal "Inherit from model"
1016 RTWMemSecDataParameters "Inherit from model"
1017 method "times"
1018 splits "1000 13000"
1019 }
1020 Block {
1021 BlockType Reference
1022 Name "split1"
1023 Tag "split"
1024 Description "Splits an AO into many sub-AOs."
1025 Ports [1, 1]
1026 Position [180, 144, 245, 186]
1027 AttributesFormatString "%<Tag>"
1028 SourceBlock "sltpda/AO class/split"
1029 SourceType "split"
1030 ShowPortLabels "FromPortIcon"
1031 SystemSampleTime "-1"
1032 FunctionWithSeparateData off
1033 RTWMemSecFuncInitTerm "Inherit from model"
1034 RTWMemSecFuncExecute "Inherit from model"
1035 RTWMemSecDataConstants "Inherit from model"
1036 RTWMemSecDataInternal "Inherit from model"
1037 RTWMemSecDataParameters "Inherit from model"
1038 method "times"
1039 splits "1000 13000"
1040 }
1041 Block {
1042 BlockType Reference
1043 Name "split2"
1044 Tag "split"
1045 Description "Splits an AO into many sub-AOs."
1046 Ports [1, 1]
1047 Position [180, 254, 245, 296]
1048 AttributesFormatString "%<Tag>"
1049 SourceBlock "sltpda/AO class/split"
1050 SourceType "split"
1051 ShowPortLabels "FromPortIcon"
1052 SystemSampleTime "-1"
1053 FunctionWithSeparateData off
1054 RTWMemSecFuncInitTerm "Inherit from model"
1055 RTWMemSecFuncExecute "Inherit from model"
1056 RTWMemSecDataConstants "Inherit from model"
1057 RTWMemSecDataInternal "Inherit from model"
1058 RTWMemSecDataParameters "Inherit from model"
1059 method "times"
1060 splits "1000 13000"
1061 }
1062 Block {
1063 BlockType Reference
1064 Name "split3"
1065 Tag "split"
1066 Description "Splits an AO into many sub-AOs."
1067 Ports [1, 1]
1068 Position [180, 359, 245, 401]
1069 AttributesFormatString "%<Tag>"
1070 SourceBlock "sltpda/AO class/split"
1071 SourceType "split"
1072 ShowPortLabels "FromPortIcon"
1073 SystemSampleTime "-1"
1074 FunctionWithSeparateData off
1075 RTWMemSecFuncInitTerm "Inherit from model"
1076 RTWMemSecFuncExecute "Inherit from model"
1077 RTWMemSecDataConstants "Inherit from model"
1078 RTWMemSecDataInternal "Inherit from model"
1079 RTWMemSecDataParameters "Inherit from model"
1080 method "times"
1081 splits "1000 13000"
1082 }
1083 Block {
1084 BlockType Reference
1085 Name "split4"
1086 Tag "split"
1087 Description "Splits an AO into many sub-AOs."
1088 Ports [1, 1]
1089 Position [180, 474, 245, 516]
1090 AttributesFormatString "%<Tag>"
1091 SourceBlock "sltpda/AO class/split"
1092 SourceType "split"
1093 ShowPortLabels "FromPortIcon"
1094 SystemSampleTime "-1"
1095 FunctionWithSeparateData off
1096 RTWMemSecFuncInitTerm "Inherit from model"
1097 RTWMemSecFuncExecute "Inherit from model"
1098 RTWMemSecDataConstants "Inherit from model"
1099 RTWMemSecDataInternal "Inherit from model"
1100 RTWMemSecDataParameters "Inherit from model"
1101 method "times"
1102 splits "1000 13000"
1103 }
1104 Block {
1105 BlockType Outport
1106 Name "Out1"
1107 Position [565, 288, 595, 302]
1108 IconDisplay "Port number"
1109 BusOutputAsStruct off
1110 }
1111 Line {
1112 SrcBlock "Standard Filter"
1113 SrcPort 1
1114 DstBlock "split"
1115 DstPort 1
1116 }
1117 Line {
1118 SrcBlock "Standard Filter1"
1119 SrcPort 1
1120 DstBlock "split1"
1121 DstPort 1
1122 }
1123 Line {
1124 SrcBlock "Standard Filter2"
1125 SrcPort 1
1126 DstBlock "split2"
1127 DstPort 1
1128 }
1129 Line {
1130 SrcBlock "Standard Filter3"
1131 SrcPort 1
1132 DstBlock "split3"
1133 DstPort 1
1134 }
1135 Line {
1136 SrcBlock "Standard Filter4"
1137 SrcPort 1
1138 Points [0, 5]
1139 DstBlock "split4"
1140 DstPort 1
1141 }
1142 Line {
1143 SrcBlock "split"
1144 SrcPort 1
1145 Points [70, 0; 0, 180]
1146 DstBlock "Mux"
1147 DstPort 1
1148 }
1149 Line {
1150 SrcBlock "split1"
1151 SrcPort 1
1152 Points [60, 0; 0, 100]
1153 DstBlock "Mux"
1154 DstPort 2
1155 }
1156 Line {
1157 SrcBlock "split2"
1158 SrcPort 1
1159 Points [70, 0; 0, 20]
1160 DstBlock "Mux"
1161 DstPort 3
1162 }
1163 Line {
1164 SrcBlock "split3"
1165 SrcPort 1
1166 Points [70, 0; 0, -55]
1167 DstBlock "Mux"
1168 DstPort 4
1169 }
1170 Line {
1171 SrcBlock "split4"
1172 SrcPort 1
1173 Points [145, 0]
1174 DstBlock "Mux"
1175 DstPort 5
1176 }
1177 Line {
1178 SrcBlock "Mux"
1179 SrcPort 1
1180 DstBlock "ltpda_timedomainfit"
1181 DstPort 1
1182 }
1183 Line {
1184 SrcBlock "In1"
1185 SrcPort 1
1186 DstBlock "Standard Filter"
1187 DstPort 1
1188 }
1189 Line {
1190 SrcBlock "In2"
1191 SrcPort 1
1192 DstBlock "Standard Filter1"
1193 DstPort 1
1194 }
1195 Line {
1196 SrcBlock "In3"
1197 SrcPort 1
1198 Points [15, 0]
1199 DstBlock "Standard Filter2"
1200 DstPort 1
1201 }
1202 Line {
1203 SrcBlock "In4"
1204 SrcPort 1
1205 DstBlock "Standard Filter3"
1206 DstPort 1
1207 }
1208 Line {
1209 SrcBlock "In5"
1210 SrcPort 1
1211 Points [15, 0]
1212 DstBlock "Standard Filter4"
1213 DstPort 1
1214 }
1215 Line {
1216 SrcBlock "ltpda_timedomainfit"
1217 SrcPort 1
1218 DstBlock "Out1"
1219 DstPort 1
1220 }
1221 }
1222 }
1223 Block {
1224 BlockType Reference
1225 Name "x12"
1226 Tag "ao"
1227 Description "Creates an Analysis object from a file."
1228 Ports [0, 1]
1229 Position [80, 68, 130, 102]
1230 AttributesFormatString "%<Tag>"
1231 SourceBlock "sltpda/AO class/ao1"
1232 SourceType "ao"
1233 ShowPortLabels "FromPortIcon"
1234 SystemSampleTime "-1"
1235 FunctionWithSeparateData off
1236 RTWMemSecFuncInitTerm "Inherit from model"
1237 RTWMemSecFuncExecute "Inherit from model"
1238 RTWMemSecDataConstants "Inherit from model"
1239 RTWMemSecDataInternal "Inherit from model"
1240 RTWMemSecDataParameters "Inherit from model"
1241 fname "/Users/hewitson/working/ltp/ltpda/software/m-to"
1242 "olbox/sltpda/test/x12.txt"
1243 }
1244 Line {
1245 SrcBlock "x12"
1246 SrcPort 1
1247 Points [0, -5; 65, 0]
1248 Branch {
1249 Labels [0, 0]
1250 DstBlock "time-domain fit"
1251 DstPort 1
1252 }
1253 Branch {
1254 Points [0, -35; 265, 0; 0, 5]
1255 Branch {
1256 Points [0, 90]
1257 DstBlock "Mux2"
1258 DstPort 1
1259 }
1260 Branch {
1261 DstBlock "ltpda_polydetrend"
1262 DstPort 1
1263 }
1264 }
1265 Branch {
1266 Points [0, 85]
1267 DstBlock "Mux1"
1268 DstPort 2
1269 }
1270 }
1271 Line {
1272 SrcBlock "eta1"
1273 SrcPort 1
1274 Points [85, 0]
1275 Branch {
1276 Points [0, -85]
1277 DstBlock "time-domain fit"
1278 DstPort 2
1279 }
1280 Branch {
1281 Points [210, 0]
1282 DstBlock "Mux1"
1283 DstPort 3
1284 }
1285 }
1286 Line {
1287 SrcBlock "phi1"
1288 SrcPort 1
1289 Points [95, 0; 0, -55]
1290 Branch {
1291 Points [0, -100]
1292 DstBlock "time-domain fit"
1293 DstPort 3
1294 }
1295 Branch {
1296 Points [200, 0]
1297 DstBlock "Mux1"
1298 DstPort 4
1299 }
1300 }
1301 Line {
1302 SrcBlock "phi12"
1303 SrcPort 1
1304 Points [120, 0; 0, -190]
1305 Branch {
1306 Points [0, -125]
1307 DstBlock "time-domain fit"
1308 DstPort 5
1309 }
1310 Branch {
1311 DstBlock "Mux1"
1312 DstPort 6
1313 }
1314 }
1315 Line {
1316 SrcBlock "eta12"
1317 SrcPort 1
1318 Points [105, 0; 0, -125]
1319 Branch {
1320 Points [0, -115]
1321 DstBlock "time-domain fit"
1322 DstPort 4
1323 }
1324 Branch {
1325 DstBlock "Mux1"
1326 DstPort 5
1327 }
1328 }
1329 Line {
1330 SrcBlock "Mux1"
1331 SrcPort 1
1332 DstBlock "ltpda_lincom"
1333 DstPort 1
1334 }
1335 Line {
1336 SrcBlock "ltpda_pwelch"
1337 SrcPort 1
1338 DstBlock "plot1"
1339 DstPort 1
1340 }
1341 Line {
1342 SrcBlock "Mux2"
1343 SrcPort 1
1344 DstBlock "ltpda_pwelch"
1345 DstPort 1
1346 }
1347 Line {
1348 SrcBlock "ltpda_lincom"
1349 SrcPort 1
1350 Points [10, 0; 0, -35]
1351 DstBlock "Mux2"
1352 DstPort 2
1353 }
1354 Line {
1355 SrcBlock "ltpda_polydetrend"
1356 SrcPort 1
1357 Points [80, 0]
1358 DstBlock "plot"
1359 DstPort 1
1360 }
1361 Line {
1362 SrcBlock "time-domain fit"
1363 SrcPort 1
1364 Points [45, 0; 0, 45]
1365 DstBlock "Mux1"
1366 DstPort 1
1367 }
1368 }
1369 }